1. Field of the Invention
The present invention relates generally to methods for forming dual damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for forming low dielectric constant dual damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants in a range of from about 2.0 to less than about 3.5. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 4.0 to about 8.0. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, such damascene methods often damage the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated damage to the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within: (1) Zhao et al., in U.S. Pat. No. 6,100,184 (a dual damascene method for forming a copper containing contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed of a comparatively low dielectric constant dielectric material to contact a copper containing conductor layer formed thereunder, while employing a conductor barrier/etch stop layer formed selectively passivating only the top surface of the copper containing conductor layer formed thereunder); (2) Grill et al., in U.S. Pat. No. 6,140,226 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant dielectric material while employing a sidewall liner layer for purposes of protecting from lateral etching a sidewall of the trench when forming contiguous therewith the via while employing the dual damascene method); (3) Huang, in U.S. Pat. No. 6,177,364 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant fluorosilicate glass (FSG) dielectric material while employing a hydrogen-nitrogen plasma treatment for purposes of passivating a sidewall surface of the dielectric layer within the corresponding trench contiguous with the corresponding via prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer); and (4) Tang et al., in U.S. Pat. No. 6,211,092 (a counterbore type dielectric etch method which may be employed when forming through a dielectric layer a dual damascene aperture employed within a dual damascene method, wherein the counterbore type dielectric etch method employs a plurality of etch steps when first forming a via through the dielectric layer).
Desirable in the art of microelectronic fabrication are additional damascene methods and materials which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated damage to the microelectronic dielectric layers.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is formed with attenuated damage to the microelectronic dielectric layer.
A third object of the present invention is to provide a damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a dual damascene aperture within a composite dielectric layer, as well as a microelectronic fabrication which results from the method. To practice the method of the present invention, there is first provided a substrate having formed therein a contact region. There is then formed upon the substrate and the contact region a blanket first etch stop layer. There is then formed upon the blanket first etch stop layer a patterned first dielectric layer having formed aligned thereupon a patterned second etch stop layer in turn having formed thereupon a patterned second dielectric layer which leaves exposed a top surface portion of the patterned second etch stop layer. Within the present invention, the foregoing series of patterned layers defines an aperture aligned above the contact region and having as bottom surfaces exposed top surface portions of the patterned second etch stop layer and the blanket first etch stop layer. Finally, there is then etched completely through the blanket first etch stop layer to reach the contact region while not etching completely through the patterned second etch stop layer to reach the patterned first dielectric layer, to thus form from the aperture a dual damascene aperture. Similarly, within the present invention: (1) the blanket first etch stop layer is formed of a first etch stop material; and (2) the blanket second etch stop layer is formed as a laminate of a second etch stop material having formed thereupon a third etch stop material.
Within the present invention, a contiguous patterned conductor interconnect and patterned conductor stud layer may be formed into the dual damascene aperture, which comprises a corresponding trench contiguous with a corresponding via which in turn reaches the contact region, while employing a blanket conductor layer deposition and planarizing method, preferably a blanket conductor layer deposition and chemical mechanical polish (CMP) planarizing method.
There is provided by the present invention a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, wherein the patterned microelectronic conductor layer is formed with attenuated damage to the microelectronic dielectric layer.
The present invention realizes the foregoing object by employing within a dual damascene method, and for forming a dual damascene aperture within which may be formed a contiguous patterned conductor interconnect and patterned conductor stud layer having formed interposed between its patterns a dielectric layer formed of a low dielectric constant dielectric material, a first etch stop layer formed of a first material and a second etch stop layer formed as a laminate of a second material having formed thereupon a third material. Under conditions where the second material serves as an additional etch stop with respect to the first material and the third material (i.e., both the first material and the second material may be etched at rates considerably faster than the second material), and when etching completely through the first etch stop layer to reach a contact region formed thereunder when forming the dual damascene aperture, there is not completely etched through the second etch stop layer to reach a first dielectric layer formed thereunder when forming the dual damascene aperture.
The damascene method in accord with the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment, as set forth below, the damascene method of the present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations and specific materials limitations to provide the damascene method of the present invention. Since it is thus at least in part a series of specific process limitations and specific materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the damascene method of the present invention is readily commercially implemented.